Power consumption in many digital logic circuits is a function of the number of signal level changes occurring in the circuit. There is low power consumption when signal levels are constant and high power consumption when the signal levels change often. For example, transmitting the sequence 10101010 requires twice the power of 10001000 and four times the power of 00001000 for a circuit where the power consumption is dependent on the frequency of transition.
In large digital chips, logic circuits may be classified as control or data flow circuits. Control circuits determine where data goes or what operation will occur. Data flow circuits handle the actual information being processed, such as implementing arithmetic operations. Data flow circuits also pass data through the circuits from one location to another, such as from a register file to a memory unit. Data flow circuit power consumption depends on the number of transitions in the data as it propagates along the data path. The power consumption of a data flow circuit can swing from near zero consumption for a bit stream with a single value to maximum consumption for a bit stream with alternating values. Power consumption in control circuits can also be subject to peaking power consumption. For example, if an address counter has a large load, it will have high power consumption at certain control code changes such as from an all 1 code to an all 0 code. Power supplies and chip cooling must be designed for maximum power consumption. This increases chip size, complexity, and cost. Current techniques for stabilizing power consumption focus on managing power consumption through the design of the particular integrated circuit family. Such measures for mitigating power consumption can limit the design and layout of components in integrated circuits as well as increasing integrated circuit complexity.
It would be desirable to have a digital logic circuit having a power consumption stabilization system that would overcome the above disadvantages.